Singular preprocessor definition needed

This is my first post, I hope to be clear enough (sorry for my eglish) and I hope to be lucky and find the answer to a very big problem.

I have a VC++ project and I need to create, during the compilation, a define that has the same name of the file that I am currently compiling.

For example, if when I am compiling a file called Main.c I need to create runtime a define

#define main 1

I do this by specifying the in Preprocessor Definitions section

$(InputName)=1

The problem is that the command above create a define

#define Main 1

instead I need the name of the file in lower case.

I thought in the beginning to create a custom task in MSBuild, but then I have discovered that it cannot be done, because the structure of the project files in C++ is still not compatible with MSBuild. How can I solve this problem

any help or suggestion is appreciated

thanks in advance
Marco

Visual C++3

Did you try the __FILE__ macro

unfortunately the __FILE__ macro is used to get the name of the file that is currently be processed.

I have to do a different thing create a define with the same name of the file I am compiling written in lowercase..

Than $(InputName) bust be all lowercase. Rename the file taht it matches!

Why don't you just type it in At the top of Main.c, write #define main 1. At the top of Util.c, write #define util 1. Etc.

thanks for the answer, but if it would be so easy probably I would have reached the solution by myself :-)

unfortunately I cannot modify the name of the files because they are shared between other projects and I have no control/power on them. I have to take "them as they are". Other ideas

thank you for the answer but I want to automatize this process, also because I have more than 100 files to manage in this way...

Tell us the reason why do you need those defines. Maybe there is another trick!

Just my two cents: 100 files are not so many. Anyhow from 7:27 AM UTC when you started digging this till now, was much more than enough time to type by hand those define, like nobugz already suggested. ;-)

I can also change manually 100 files. For sure I will not stop my development due to this problem. But I would also like to know if it is possible to achieve in some way the desired solutions...and, as I thought in the beginning, probably the answer is no.

I know of no way to automatically do this in a makefile - if you really need to do this then I would look at embedding a small perl script in your makefile.

interesting... do you have any links with some examples how to embed custom action into the make file

It's curious why one would want to create dependencies that compile in potentially 100 different ways depending on which file is being compiled.

There's no information on what you're actually doing and what performance considerations you have. But for the sake of brainstorming, I wonder if you can manage these these different contexts at runtime. At certain call sites, pass the value of __FILE__ to the function whose behavior shall differ. This function uses a hash table (or specifically std::map) to determine the context.

Brian

Better yet, why not just create new functions and/or arguments to do the specialization There's a reason why people say "macros are evil." :)

I know that it's curios, and I don't like too to use this solution, but I have no chance.

I didn't explain the reason behind this before, because is really complex to explain and specific for the project that I am developing.

In brief, I have to create an "emulator" of a microcontroller. The firmware of the microcontroller is written in C, and I have to compile the same code in Visual Studio.

The people which have created the firmware has implemented in the code a conditional compilation that uses the name of the file in compilation to do different things. They creates this preprocessor define using a special "make".

I have to reply the same behavior in Visual Studio, and this is the reason of my question here...